High-performance phase-locked loops (PLLs) require accurate sensing and correction of a phase and frequency error between a reference clock signal and a feedback clock signal. Typically, a PLL includes a phase-frequency detector (PD), a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and optionally a frequency divider. The PD senses the phase and frequency error and generates timing signals, which are used to generate an output current in the charge pump. The timing signals can consist of up pulses or down pulses that the charge pump receives to increase or decrease the output current over time. These currents are then integrated by a loop filter to create a control voltage, which is input to the VCO. The control voltage adjusts the frequency of the VCO to generate an output signal that is in phase and having a same frequency as the reference clock signal. The output signal can be fed back through the frequency divider to generate the feedback clock signal. Ideally, a plot of the control voltage as a function of the phase error should produce a linear response over an operating cycle where the PLL operates as expected.
Conventional charge pumps have current sources and current sinks along with switching devices used to control current flows through the current sources and current sink. The charge pump receives the timing signals, such as the up pulses and down pulses, and switches these switching devices on or off to change the output current of the charge pump. For example, when the feedback clock signal leads the reference clock signal, the current sink reduces output current in response to the down pulses so that the control voltage is decreased. The decrease in output voltage over time mitigates the phase lag. When the reference clock signal leads the feedback clock signal, the current source increases the output current in response to the up pulses so that the control voltage is increased. The increase in output voltage over time mitigates the phase lag. When the PLL is locked, the current source and the current sink keep the output current constant so that the control voltage does not change, and accordingly, the output signal stays in phase with the reference clock signal.
The charge pump generally operates at a nominal supply voltage. The supply voltage provides power to the transistors in the charge pump, which provide the output current to the VCO. The transistors generally have a nominal device rating that is below the supply voltage. Accordingly, the output voltage range of the charge pump is generally limited by the voltage operating ranges of the transistors. Consequently, the output voltage range is generally lower than the supply voltage. Attempting to increase the output voltage of the charge pump to a greater range by increasing the supply voltage can cause the transistors to break down.
Current prior art methods to increase the output voltage range of a charge pump generally introduce a loading on the charge pump which decreases output impedance of the charge pump. The decrease in impedance reduces the phase lock accuracy of the PLL. Moreover, the VCO gain is largely dependent on the output voltage range. The VCO, which receives the output current of the charge pump, must generally compensate for the small output voltage range of the charge pump. In practice, a conventional VCO compensates for the small output voltage range of a charge pump by providing a higher gain which can introduce noise, thereby increasing phase errors and sacrificing phase lock accuracy. A need therefore exists for increasing the output voltage range of a charge pump while maintaining linear operation without loading the output of the charge pump.